Andrew Butt

@nathanielnrn @sampsyo @rachitnigam I updated this issue with all the bugs I found and explanations. Let me know if you have any questions, I have a pretty good grasp on...

@nathanielnrn The kernel.xml doesn't really "interface" with the verilog per-say, it is just a simpler description of the underlying verilog that XRT uses to know how to interact with the...

That's actually the Control_axi instantiation, so 32 is the correct value there. The issue is with the memory module here: https://github.com/cucapra/calyx/blob/943a50ebdb1533dabfc6f82f638b43d5744fe7c0/src/backend/xilinx/toplevel.rs#L50 There is a 512 there, but there's also a...

Sounds great. A few more questions I have: 1. Where should this generator be implemented? Within the Calyx Rust source? 2. Is this a "JIT" generator or an "AOT" generator?...

Thanks @sampsyo! I was actually in the middle of typing out some more questions but that answers a lot of them. That plan sounds like a reasonable method to move...

Here is a prototype of the memory primitive generation stuff: https://github.com/andrewb1999/calyx-memgen-prototype. I haven't implemented everything yet, specifically rams with a latency greater than 1 and multidimensional rams, but this should...

Also, is there some way for fud to include external verilog? (i.e. the verilog definition of the primitive) If not, that's something we should look at adding.

FYI, this exists: https://github.com/alexforencich/cocotbext-axi. I've used it before with some success but it can be a little challenging to get working. My main suggestion here is to connect the m_axi...

Just as an FYI, I run into this same issue in yosys when running very large designs and I have another memory intensive application open in the background. It would...

@mithro Is there a tar available with a stable a200t rr graph/architecture? I'm interested in getting some other people to use the nexys video with symbiflow, so I would be...