Amin Mohaghegh
Amin Mohaghegh
There is a member variable in *t_pb* named *pb_route*. This is a map-like data structure, and its key is the logical number of a pin. Thus, I can assume that...
In this PR, the routing resources (pins & connections) inside of the tiles, to which netlist's block has been mapped to it, are added to the RR Graph. To enable...
When I uncomment VERBOSE flag in "vpr_types.h", I can't build VPR. It seems the problem is mainly related to some parts of the placement code. I had to comment the...
In router_lookahead_map ([this line](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/a7cd8f99740d64acb92c470fd5b9069c1f0e04c5/vpr/src/route/router_lookahead_map.cpp#L329)), the expected delay is multiplied by (1-criticality). It seems backward to me. I think the delay should be multiplied by the criticality factor, and congestion should...
- Add the scaled delay from the "koios_3d" benchmark into the 3D SIV-like architecture. The inter-die delay is calculated by multiplying the delay of the L4 segment by the ratio...
In this PR, the ".bin" extension has been added as an acceptable file extension for the router lookahead file.
When attempting to execute run-flat on Koios benchmarks using VPR, the software crashes.
This is a work in progress. The full description will be written soon.
I tried to implement `stereovision0.v` on `simple-7series.xml`. I ran this command: `run_vtr_flow.py stereovision0.v simple-7series.xml` and got this error message: `simple-7series/stereovision0 Error: Executable yosys failed full command: /usr/bin/env time -v /home/mohagh18/vtr-verilog-to-routing/build/bin/yosys...
There is a function named "sync_netlists_to_routing." This function synchronizes the results of packing and routing. During the routing, the pin that a net is connected to may change, and this...