Amin Mohaghegh

> Nightly test 1 results has a few QoR failures (8) but they look benign: > > * one small circuit (mult113) has a wider channel width > * one...

@vaughnbetz : I think this PR is finally ready to land :)

> @amin1377 : some conflicts and failures to resolve now. I tried a lot of things to figure out what is causing the memory increase when flat_routing is **not** enabled....

> A 4% memory increase isn't a deal breaker, but it's good to try to find it if it is unexpected. Going from short->int will have some impact, so might...

> A 4% memory increase isn't a deal breaker, but it's good to try to find it if it is unexpected. Going from short->int will have some impact, so might...

> @amin1377 : can you attach the latest QoR results (earlier ones are out of date te? Also, I believe the 4% memory footprint increase is now gone based on...

The script is still not working for me. I was wondering whether the issue is solved for you. @jmah76

I just reverted the changes made in [PR#2108](https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/2108), and it works now!

@jmah76: It is working (at least for me.) Thanks! @vaughnbetz: I think it is safe to merge it.

> Great, thank you so much! The relavent PR is #2122 . Yeah, I also meant PR #2122