vtr-verilog-to-routing
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20 hours ago •
verilog-to-routing
verilog-to-routing
Inconsistency in pb_route data structure
There is a member variable in t_pb named pb_route. This is a map-like data structure, and its key is the logical number of a pin. Thus, I can assume that the key of an entry to this data structure should be equal to the pb_graph_node.pin_count_in_cluster (this is the actual logical number assigned to each pin). However, when I tested it, as illustrated in the attached image, it shows that the assertion will not hold true.
arguments:
architecture file : vtr_flow/arch/timing/EArch.xml circuit: vtr_flow/benchmarks/blif/tseng.blif route_channel: 100
@vaughnbetz @MohamedElgammal
