Xiretza

Results 49 issues of Xiretza

Hi! Please create a new release tag and push it to crates.io. The latest version at this time, [0.7.0](https://github.com/1wilkens/pam/releases/tag/v0.7.0), is ancient and bears little resemblance to git master, which has...

[v.1.4.0](https://github.com/vivien/i3blocks-contrib/releases/tag/v1.4.0) states that "i3blocks-contrib will now follow the release schedule and have corresponding version numbers to i3blocks", but there is no corresponding -contrib release for [1.5](https://github.com/vivien/i3blocks/releases/tag/1.5) yet.

Unless I'm misinterpreting something, using `BuildExtension` as `cmdclass['build_ext']` in `setup.py` makes any non-cmake extension modules completely ineffective, because `BuildExtension.run()` simply ignores them: https://github.com/diegoferigo/cmake-build-extension/blob/2c3d822e40fe3fd2d769ad09dba367e6617dcc82/src/cmake_build_extension/build_extension.py#L82 Is my understanding correct? How would I...

help wanted

The only way to use this thing is to unpack release tarballs, how to get one of those from just the source tree is completely undocumented. This makes the software...

See https://github.com/blog/1547-release-your-software. Basically tag the master branch, and then add the packaged software as a binary to your release. Having a completely different branch for "releases" is quite ugly.

`DJANGO_STATIC_ROOT` is required in order to run `collectstatic` in a packaging environment - manually specifying it as an environment variable should always override any config files that may exist. This...

If a user installed etesync using the trial license, then never renewed that license but still kept etesync installed, any modifications made to contact/calendar entries after expiration of the license...

**Description** When given a memory with a write port that writes to only a subslice of a data word at a time, ghdl does not infer appropriate byte-enables unless the...

Feature: Synthesis

**Description** If a memory's write enable is gated by a `case` block instead of a simple `if`, memory inference fails. **Expected behaviour** Memory is inferred correctly, no matter how complex...

Feature: Synthesis

**Description** When a memory with an async write port is attempted to be inferred, ghdl crashes instead of producing an error message. **Expected behaviour** GHDL produces an error message explaining...

Bug
Feature: Synthesis