Xiretza

Results 49 issues of Xiretza

The hardware and cpu ports' valid signals can not be made dependent on their own ready signals, since this creates combinatorial loops. This should be unnecessary anyway though, the only...

```pycon >>> from collections import defaultdict >>> dd = defaultdict(list) >>> dd >>> dd.items() Traceback (most recent call last): File "", line 1, in AttributeError: 'defaultdict' object has no attribute...

It would be great to be able to omit the allocation of the tables in memory-constrained environments and instead fall back to generating the value for each byte on demand.

The "latest" files in the GCS bucket, e.g. https://storage.googleapis.com/symbiflow-arch-defs-gha/symbiflow-toolchain-latest point to an old version of the toolchain (currently build 597 of fb1b251a from 2022-03-22), which makes it impossible for me...

in-progress
type-infra
github_actions

GCC 11 [updated](https://gcc.gnu.org/gcc-11/changes.html) the default `-std=` for C++ to `gnu++17`. This causes abseil (which specifies no explicit `-std=`) to be built as C++17, while the rest of prjxray is build...

The script is now installed to `/usr/bin`, works when called from any directory, and is also used in the install script to avoid code duplication.

The project currently uses a rather unconventional in-tree build workflow (I'd never encountered it before in several years of python distro packaging), and I haven't yet been able to find...

Enhancement
CI: Github Actions
Discussion
f4pga (python)

/kind bug **Description** Commands run from inside `podman build` have no IPv6 access, while the same commands run from `podman run` work fine. **Steps to reproduce the issue:** `echo -e...

kind/bug
stale-issue
Buildah
network

- ghdl/ghdl@8789de96 - ghdl-yosys-plugin 6ef4d46 - YosysHQ/yosys@3cb3978ff The following file: ```vhdl :file: ent.vhd library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; entity ent is port ( clk : in std_logic; y : out...