synth: memory inference does not recognize byte-enables in some cases

[Xiretza]

Description When given a memory with a write port that writes to only a subslice of a data word at a time, ghdl does not infer appropriate byte-enables unless the sub-slices are iterated over explicitly, and falls back to register-based storage instead.

Expected behaviour Memory inference recognizes this pattern as a byte-enable and successfully infers the memory.

How to reproduce?

library ieee;
use ieee.std_logic_1164.all;

entity ent is
	generic (
		DEPTH : positive := 256
	);
	port (
		clk: in std_logic;

		write_enable: in std_logic;
		write_address: in natural range 0 to DEPTH-1;
		write_byte: in natural range 0 to 3;
		input: in std_logic_vector(7 downto 0);

		read_address: in natural range 0 to DEPTH-1;
		output: out std_logic_vector(31 downto 0)
	);
end entity;

architecture a of ent is
begin
	process(clk)
		type memory_t is array(0 to DEPTH-1) of std_logic_vector(31 downto 0);

		variable memory : memory_t;
	begin
		if rising_edge(clk) then
			output <= memory(read_address);

			if write_enable then
				memory(write_address)((write_byte+1) * 8 - 1 downto write_byte * 8) := input;

				-- the following works:
				/*
				for i in 0 to 3 loop
					if i = write_byte then
						memory(write_address)((i+1) * 8 - 1 downto i * 8) := input;
					end if;
				end loop;
				*/
			end if;
		end if;
	end process;
end architecture;

ghdl synth --std=08 ent.vhdl -e ent |& grep 'found RAM'

Context Please, provide the following information:

• OS: Arch Linux
• Origin:
  • Built from sources: a952de22c

[umarcor]

Ref: #1782.