PeakRDL-regblock
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SystemRDL
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Dear PeakRDL Development Team, ``` //-------------------------------------------------------------------------- // Address Decode //-------------------------------------------------------------------------- typedef struct { // Code not shown } decoded_reg_strb_t; // Code not shown always_comb begin // Code not shown for(int...
Does this exporter have some configuration related to this topic? Here is the situation, we have 3 rdl files, each of them is an addrmap contains some regs which accesswidth...
Different take than the VHDL request - I'm instantiating the SV output in a VHDL design. If I take the SV package and make a VHDL equivalent (records that match...
I added user-defined properties for specifying the CPU interface. The properties are `cpuif` and `addrwidth`. The command line still has the highest priority for backward compatibility. Example. ```systemrdl addrmap top...
Is it possible to add an indication for unauthorized read/write (or maybe it already exists and I missed it...) For example, let's say that a field/reg is defined as sw=w,...
Can we add a user-defined property to enable the specification of the cpuif type from the SystemRDL code as well as from the command line? This would also make it...
See example in https://github.com/SystemRDL/systemrdl-compiler/issues/193 Current implementation will silently emit colliding output, or even reuse an incorrect typedef. Monitor for this and emit an error if it occurs. Ideas for fix:...
Title is pretty self-explanatory. Add code generation support for registers that are described as aliases.
A common design pattern is to implement an address region that broadcasts write operations to multiple registers. This saves on software cycles since a single SW write can be used...
I done a series of pull requests in Verilator in order to support the code regblock is generating. In the next release 5.12 I believe most of the things will...
