Arjan Bink
Arjan Bink
Hello, I am defining (for ease of discussion) ‘Zicnt’ to be the name of the specification contained in Chapter 10 of the ‘Unprivileged ISA’ spec. The treatment of the Zicnt...
Alternative fix for the '32-bit slave access to Abstract Data' issue reported in https://github.com/pulp-platform/riscv-dbg/pull/27 more inline with the writing style recommended by @bluewww Signed-off-by: Arjan Bink
Fix for #58 - Added bus error for non-supported sbaccess values - Corrected bus error code for non-supported sbaccess values - Added bus error for misaligned SBA access attempts Signed-off-by:...
The functionality related to the dmihardreset bitfield of the dtmcs register has not been implemented
The riscv-dbg contains a clock domain crossing implemented inside dmi_cdc.sv. clk_i and tck_i are allowed to be asynchronous to each other (please correct me if I am wrong about this)....
Update according to https://github.com/openhwgroup/cv32e40x/pull/680
This is to match the CORE-V-XIF specification. Also all other use of 'parameter int' does not make sense and should be changed into 'parameter int unsigned'. This applies to the...
The following code needs explanation (and/or RTL changes) about: - Why !interrupt_allowed and !nmi_allowed are needed - Why !debug_allowed is needed ctrl_fsm_o.halt_id = ctrl_byp_i.jalr_stall || ctrl_byp_i.load_stall || ctrl_byp_i.csr_stall || ctrl_byp_i.wfi_stall...
# Template for Task Issue Tasks are defined, assigned and tracked as GitHub Issues. ## Task Title A clear and concise description of the Task. This can go in the...
Currently stalling related to CSR operations is very conservative. We should however take care that no non-needed stalls are intrdocuced for thw following scenarios: - Back to back CSR reads...