Unclarity on whether Zicnt (Unpriv spec chapter 10 Counters) related CSRs are mandatory or not

[Silabs-ArjanB]

Hello,

I am defining (for ease of discussion) ‘Zicnt’ to be the name of the specification contained in Chapter 10 of the ‘Unprivileged ISA’ spec.

The treatment of the Zicnt CSRs is quite ambiguous in the RISC-V privileged and unprivileged specs because of the following statements:

• Chapter 9 “Zicsr” of Unpriv spec: “The counters and timers are no longer considered mandatory parts of the standard base ISAs, and so the CSR instructions required to access them have been moved out of the base ISA chapter into this separate chapter.

This seems to imply that a RISC-V compliant implementation could just treat CSR instructions accessing the ‘counter and timer CSRs’ defined in Zicnt as illegal instruction

• Section 3.1.2 of the Priv spec: “The cycle, instret, and hpmcountern CSRs are read-only shadows of mcycle, minstret, and mhpmcountern, respectively. The time CSR is a read-only shadow of the memory-mapped mtime register.”

This might imply that cycle, instret, hpmcountern, and time CSRs are mandatory.

My interpretation of the official RISC-V specs with respect to Zicnt is the following (could somebody please confirm or correct these statements?):

• Zicnt is an optional extension that deals only with CSRs 0XC00-0xC1f (and 0xC80-0xC9F for RV32), so (if that is true) it is possible to make a RISC-V compliant ‘M-mode only core including Zicsr’ implementation without implementing any of the Zicnt CSRs (and triggering an illegal instruction exception upon attempted access to these CSRs). Similarly, it should then be possible to make a RISC-V compliant ‘M/U-mode core including Zicsr’ implementation without implementing any of the Zicnt CSRs (and triggering an illegal instruction exception upon attempted access to these CSRs).

• The ‘Machine Counter/Timers’ (i.e. CSRs 0xB00, 0xB02-0xB1F (and 0xB80, 0xB82-0xB9F for RV32I) are a mandatory part of every architecture that is ‘compliant to the current RISC-V privileged architecture’ (independent of whether Zicnt is included or not)

Assuming above is a correct interpretation, then I have a follow up question on what would be allowed for a compliant RV32E implementation. The mhmcounter3..31 are mandatory but are clearly specified as WARL and are allowed to be implemented as ‘read as 0 always’. mcycle(h) and minstret(h) (i.e. 128 flip-flops and two associated 64-bit counters) are not explicitly defined as WARL and are therefore always required to be fully implemented and will therefore represent a mandatory significant part of the area of a compliant RV32E implementation; is that interpretation correct?

It would be nice if table 2.2-2.5 in the Privileged spec would mention which CSRs are actually mandatory based on what condition (extension).

(This question is related to https://github.com/riscv/riscv-isa-manual/issues/543, but that issue did not result in a clear answer to the stated questions)

Best regards, Arjan