Arjan Bink
Arjan Bink
Some of the Xpulp opcodes have been chosen such that upstreaming of the related tool changes will become impossible unless we change some opcodes. Ideally only 'custom opcodes' are used...
The following assertion in cv32e40p_hwloop_regs.sv does not pass Formal (this was already reported in the PR review, but not fixed; likely assumes need to be made explicit (but conservatively marking...
Currently there is no documentation about this interface in the User Manual. I added the core-v-docs/cores/cv32e40p/user_manual/source/apu.rst file to start the documentation for this feature including a list of the associated...
The original RI5CY used to have an error pin for its instruction and data bus interfaces to signal bus errors. Unfortunately these were removed once the PMP was introduced. Proposal...
As CV32E40P does not have internal cache(s) the FENCE.I instruction only flushes the internal pipeline and prefetch buffer. For systems with an external (non-coherent) cache a 'software-directed cache-flushing followed by...
In https://github.com/pulp-platform/riscv/issues/161 Haugoug proposed an enhancement for stack overflow checking during **simulations**. This enhancement request is also about support for stachk overflow checking, but this time it is aimed at...
Summary: A load or store executed in User mode can get its privilege promoted to Machine mode (e.g. when followed by an ECALL instruction). Similarly a (multi-cycle) load store executed...
This issue will be used to provide an overview of open issues related to CV32E40X/CV32E40S Imperas ISS. The list will be continuously updated. Issues that exist on both CV32E40X and...
I issued the following pull requests: https://github.com/openhwgroup/core-v-verif/pull/1220 https://github.com/openhwgroup/core-v-verif/pull/1221 They are to make core-v-verif compile after changing mimpid_i[31:0] to mimpid_patch_i[3:0] in both CV32E40X and CV32E40S and after adding the integrity attribute...
core-v-verif is using quite outdated RISC-V compliance tests. By now (i.e. end of last year) ‘framework 2’ has been introduced and ‘framework 3’ is being worked on, see https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/Luf6uWuAAlU. Issue...