veriloggen

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Supporting multiple outstanding DMA requests

1

shtaxxx

shtaxxx

Better Documentation/Tutorials

6

So the examples are useful for somethings but say if I want to have nested if statements or make something that generates this verilog: ```Verilog reg signed [width:0] x [0:width-1];...

xd009642

How to use from_verilog function in veriloggen

1

Hi, I am trying to use this package for creating IPXACTS from verilog files. Can it be done? If so, is it by from_verilog function or somehow?

bhargav3333

realtime monitoring of simulation output

1

Hi, On my platform (macOS Sierra 10.12.5, vvp 11.0, iverilog 11.0) the display=True option of simulation.run doesn't provide realtime output when using the iverilog simulator. The simulation runs, but no...

sgherbst

shtaxxx

shtaxxx

When you run the following, the task call part is not generated as expected ```python import veriloggen as vg module = vg.Module("task_module") clk = module.Input("CLK") a = module.Input("a") init_task =...

Hikakkun

``` from __future__ import absolute_import from __future__ import print_function import sys import os import collections # the next line can be removed after installation sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))) from veriloggen import *...

darcy-wu

# Adding Support for OpenLane ## Introduction Veriloggen has the potential to synthesize hardware for both FPGAs and ASICs. However, its design is not optimal for ASICs because it was...

mu2519