veriloggen
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Supporting multiple outstanding DMA requests
Two DMAs in the following thread code should be overlapped.
def ctrl():
myaxi.dma_read_async(local_ram, laddr0, gaddr0, size0)
myaxi.dma_read_async(local_ram, laddr1, gaddr1, size1)
myaxi.dma_wait()
To support multiple outstanding requests, unissued request queue and issued request queue will be required respectively. The similar mechanism had been implemented in PyCoRAM.