Steven Herbst

A framework for FPGA emulation of mixed-signal systems

sgherbst

Automatic generation of real number models from analog circuits

sgherbst

Minimal SKY130 example with self-checking LVS, DRC, and PEX

sgherbst

Determines the modules declared and instantiated in a SystemVerilog file

sgherbst

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

sgherbst

Python library for parsing module definitions and instantiations from SystemVerilog files

sgherbst