Jinyan Xu

Hi, we recently tested this commit using our hardware fuzzer, the arithmetic function is consistent with the spike implementation, nice work! We detected some mismatches in some corner cases: -...

Sorry for the confusion. Since misa is writable, for the extended instruction set we need to detect whether the corresponding extension is turned on during execution, which means that there...

The register difference is some register has been optimized in Verilog, though I put my transform behind VerilogEmitter, there is still some dead code. I find some registers defined in...

Thanks, the point we wanted to confirm was the mismatched *tval. And sorry for the confusion in my description, we wanted to point out that the ecall/ebreak triggered in any...

Hi, we believe this is not a bug. The reason causes this problem is that cva6 has cache while spike doesn't. If the software modifies the code segment without a...

Nope, I believe this is a legal implementation difference in the specification. You can find more details in Volume 1 v20191213 Section 8.3 Eventual Success of Store-Conditional Instructions

Following is the test case we use, in this program we add a breakpoint to the 0x80000178 and specify the size field is 3. This is possible because the manual...

After testing, spike no longer exits due to the breakpoint.

Sorry for the late reply, if I remember correctly, there is a race condition. As I mentioned, considering a 2-element FIFO. ``` # init itePtr = 0, nextWrite = 1...

Yes, but the priority of the misaligned exception is also wrong, which is outside of the load_slow_path function.