Writing should have priority over reading

[Phantom1003]

Suppose there is only one element in the FIFO (depth is 2), both read and write happens, the emptyReg should be false after this cycle

[schoeberl]

Can you explain the difference? These are all concurrent statements.

[Phantom1003]

Sorry for the late reply, if I remember correctly, there is a race condition.

As I mentioned, considering a 2-element FIFO.

# init
itePtr = 0, nextWrite = 1
readPtr = 0, nextRead = 1
# write something
writePrt = 1, nextWrite = 0
readPtr = 0, nextRead = 1

Although all statements are executed in parallel in chisel, if they occur at the same time, the later one will actually be used. If both read and write happens, the emptyReg will be assigned to true (nextRead === writePtr). But it should be false, so I change the order.

It looks like the latest code has fixed this race condition, I will close this pull.