Jinyan Xu
Jinyan Xu
When access a page without A or write a page without D, hardware have 2 choices 1. raise a exception 2. set bits qemu choose the second way, if we...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Our co-simulation framework found that the exception type of...
Our co-simulation framework found that the mstatus.sd field does not update immediately after mstatus.fs field is dirty. In the following test case, we set mstatus.fs field to initial(0b01), and then...
Our co-simulation framework found that the exception type of address translation PMA violation is incorrect. In the following test case, we modify a non-leaf (level 2) PTE to zero, which...
Our co-simulation framework found that the exception type when access/load/store an illegal virtual address is incorrect. In the following test case, we flipped the MSB of a legal virtual address...
Our co-simulation framework found that the `*tval` of `ecall/ebreak` is incorrect. In cva6, after `ecall/ebreak`, *tval will set to the machine code of the `ecall/ebreak` instruction. In the following test...
Our co-simulation framework found that cva6 will truncate the address to use, specifically ignoring the highest 8 bits for pc and the highest 32 bits for load/store. Let's take the...
**Type of issue**: bug report **Impact**: unknown **Development Phase**: proposal **Other information** Our co-simulation framework found that the exception type of address translation PMA violation is incorrect. In the following...
**Type of issue**: bug report **Impact**: unknown **Development Phase**: proposal **Other information** Our co-simulation framework found that the exception type of address translation PMP violation is incorrect. In the following...
### What is the current behavior? I want to write a transform to collect all the register generated At first, my transform is under VerilogEmitter: ``` firrtl.stage.transforms.Compiler ├── firrtl.passes.ExpandConnects$ ├──...