chisel-cheatsheet
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freechipsproject
Adding Register Vec initialisation
[a copy from chisel repository issue]
Type of issue: documentation
Impact: no functional change
Development Phase: request
Other information Is it possible to add Vec initialization ?
For example, here a vec initialization of a register file of 31 UInt registers of 32bits width.
val regfile = RegInit(VecInit(Seq.fill(31)(0.U(32.W))))
