PSL sequence implication parsing error

[Blebowski]

I run into trouble analysis PSL assertions that contain sequence implications.

E.g.:

library ieee;
use ieee.std_logic_1164.all;

entity psl_sequence_implication is
end entity;

architecture tb of psl_sequence_implication is

    signal clk : std_logic;

    signal a,b : std_logic;

begin

    -- psl default clock is rising_edge(clk);

    -- psl asrt_1 : assert always
    --  {a = '1'} |=> {b = '1'};

end architecture;

I get:

nvc -a --psl psl_sequence_implication.vhd 
** Error: unexpected | while parsing assert directive, expecting one of @ or ;
    > psl_sequence_implication.vhd:18
    |
 18 |     --  {a = '1'} |=> {b = '1'};
    |                   ^ this token was unexpected

The code analyses OK in GHDL and Aldec.