Ondrej Ille
Ondrej Ille
Hi, the idea comes from experience with Vivado in 2021 (Pro edition). I was working on a block that had a VHDL clocked process decoding state of an FSM and...
Hi @amykyta3, sorry for long time without reply. We were chasing tape-out, so I got to it only now. We took one of our blocks, and we replaced ORDT generated...
Agreed, this is a better approach. `SYNTHESIS` define sounds good.
With the https://github.com/SystemRDL/PeakRDL-regblock/issues/103, I sort of agree (despite the personal preference) that the "tool should handle it". I think here, you are not correct. I have not seen DC to...
Would you accept contribution of this feature assuming that it would not pollute the peakRDL code-base ? This will affect "reg-block" tool only.
Looking at reference manual, there are some hints on the DC could be doing this multi-stage, I need to check. However, I still would prefer doing this by hand.
Hi, may I mask what is the status and plans here ? Is CW340 supposed to replace the CW310 for the purposes of OT SCA ? I see that the...
Thanks @nasahlpa. My thinking was precisely opposite. Since ultra-scale has better clocking, it would allow to emulate e.g. per-IP clock gate enable as on the ASIC, and therefore not to...
So it is good to have the information instead of going completely wrong direction :)
Hi, I will prepare a reproducer that compares these two.