Ondrej Ille

Ok, thanks for explaining. I only knew that Kicad is trying to use sparselizard for some basic SI/PI PCB stuff. As for me, I am really a SI noob (at...

Or does the tools like PrimeTime account for actual logic values on adjacent wires (IMHO they can't they dont simulation functionality of the circuit)? I mean, lets have two adjacent...

@Ceridli, could you maybe send me some scientific articles / technical materials about this? I would like to understand how it works in STA engines.

Well there are two options I think: - At the end of each non-delta cycle - Each time when variable is assigned (which can be multiple times during single simulation...

OK, I see, then dumping at the end of non-delta cycle seems more reasonable. As for the GTKWave, I don't know. I have looked into it long time ago, and...

Toggle coverage bug: ``` ==================================================== ** Note: initialising [10ms +23412kB] ** Note: loading top-level unit [7ms +5100kB] ** Note: elaborating design [3ms +516kB] ** Note: generating intermediate code [2ms +0kB]...

Hi, no problem, I don't expect to get it merged right away anyway (see the bug above which occurs when signal in port map is not directly mapped to signal...

> As well as the HTML report, could you also add a coverage sub-command like `--summary` that prints a text summary? That will make it much easier to do some...

OK, @nickg , now the thing is ready for review. I managed to elaborate and run bit of my fairly complex design (CTU CAN FD IP core - so far...

I also expected worse, but its only elaboration, I would be curious about the simulation. Individual coverage types have following results: No coverage: ``` Elaborating: ** Note: initialising [16ms +23244kB]...