Ondrej Ille

Thanks @JimLewis that is appreciated. I will go on with integration on NVC side and rebase my OSVVM updates once the changes from you are available.

Hi, @amykyta3 do you have any plan / roadmap on when could this be available ? We at [Tropic Square](https://github.com/tropicsquare) are currently evaluating PeakRDL toolchain as we would like to...

Hi @amykyta3 , thanks for your reply. Its good to know that the you aim to continue with the project. I hope you had a good rest (the penguin is...

A simplified version would be without counters containing only the assertion state. Some of this data would be needed though in the VHDL2019 Assert API. The state could be displayed...

Any clue on what to do with this ? I like HAL, and I would like to try to use it instead of commercial equivalent called GateVisionPRO, but the fact...

Thanks for the reply. In a typical "digital on top" ASIC development, some analog macros such as "voltage regulators" may not even have logic function. A `.lib` file for such...

I understand. I will try to explain my use-case. I was trying to evaluate HAL as a possible alternative for gate-level debugger / netlist viewer. If you are faimiliar with...

> Funny that you mention Quartus from Altera since I started only days ago to build a gate library for a Cyclone V netlist. I am still a newbie in...

Hi @likeamahoney, maybe I got it wrong, but doesn't the following: ``` The state-dependent paths that correspond to the ifnone path may be either simple module paths or edge-sensitive paths...

Oh, I see, thanks. It seems like inconsistency in the LRM itself, or not ? The grammar says: ``` state_dependent_path_declaration ::= if ( module_path_expression ) simple_path_declaration | if ( module_path_expression...