Angelo Jacobo
Angelo Jacobo
FPGA_OV7670_Camera_Interface
Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
FPGA_RealTime_and_Static_Sobel_Edge_Detection
Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
FPGA_Book_Experiments
My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
RISC-V
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
FPGA_SDRAM_Controller
SDRAM controller optimized to a memory bandwidth of 316MB/s
OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
UberDDR3
Opensource DDR3 Controller
ULX3S_FPGA_Camera_Streaming
Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
ULX3S_FPGA_Sobel_Edge_Detection_OV7670
Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board