AngelaGonzalezMarino

Fixed in mmu unified https://github.com/openhwgroup/cva6/pull/1851

Thanks!

These were the tests/checks used: • Test the Sv32 behaviour of the single MMU design in CV32A6 with the booting of 32-bit Yocto Linux on the Diligent Genesys 2 board....

> I tried the unified MMU with and without shared TLB on FPGA. > > When shared TLB is activated for CV32A6 and CV64A6, it works well, Linux boot without...

> For CV32A6, I used cv32a6_ima_sv32_fpga configuration. > > To deactivate shared TLB, I modified following parameters in cv32a6_ima_sv32_fpga_config_pkg.sv > > localparam CVA6ConfigInstrTlbEntries = 16; localparam CVA6ConfigDataTlbEntries = 16; localparam...

@ninolomata Thanks a lot for the review! I have addressed most comments with the latest commits. The remaining ones are about splitting the signals in interfaces or not. What I...

> Great work, @AngelaGonzalezMarino. I have a few suggestions: > > 1. In section _"Flushing TLB Entries"_, HFENCE cases need to mentioned explicitly. > 2. Please correct me if I'm...

> Now, it looks good to me. Only the diagram of nested translation is remaining. Thanks! The diagram from @ninolomata is now added to this documentation

@ninolomata can you please check if this is the right fix? Thanks!

@ninolomata can you confirm that this is the correct tval? Thanks!