Possible issue with ASID on CV32A6

[atrogerTHALES]

There is probably an issue with the ASID signal in the SV32's MMU for the CV32A6.

1. ASID's width is hard coded in cva6_tlb_sv32.sv and does not use the ASID_WIDTH parameter (which is used by the input ASID signal though). It should probably be modified to use that parameter.

    input  logic [ASID_WIDTH-1:0]   lu_asid_i,

 // Sv32 defines two levels of page tables
    struct packed {
      logic [8:0]            asid; //9 bits wide
      logic [9:0]            vpn1; //10 bits wide
      logic [9:0]            vpn0; //10 bits wide
      logic                  is_4M;
      logic                  valid;
    } [TLB_ENTRIES-1:0] tags_q, tags_n;

2. The ASID_WIDTH parameter in ariane_pkg.sv is set to 1 instead of 9 as per the RISC-V specs. It should be changed to 9 for XLEN = 32.

    localparam ASID_WIDTH    = (riscv::XLEN == 64) ? 16 : 1;

RISC-V specs :

[MikeOpenHWGroup]

@ASintzoff, @sjthales, this Issue is very old, but looks like an RTL bug. Please assign someone to investigate.

[ASintzoff]

As @sjthales (developer of Sv32 MMU) is far more competent than me on this topic, I let him tackling the issue. Thanks.

[jquevremont]

@fatimasaleem, can 10xEngineers help with this possible MMU bug?

[fatimasaleem]

Spec says "The number of ASID bits is unspecified and may be zero." so setting ASID_WIDTH to 1 is not a bug IMHO. But yes the tag struct should use ASID_WIDTH.

[AngelaGonzalezMarino]

Fixed in mmu unified https://github.com/openhwgroup/cva6/pull/1851