AndrewD
AndrewD
It would be useful to update Nuttx libcxx to [14.0.6](https://github.com/llvm/llvm-project/releases/tag/llvmorg-14.0.6) or even the latest 15.0.0 release to make newer C++ library features and fixes available. Even 15.0.0 (released Sep 6th)...
We feel it would be useful to have Nuttx as a target for LLVM. Has anyone attempted this? It looks quite feasible to implement and it appears llvm has been...
The current memory map allows for 32 CSR locations: `INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).` This can be expanded to...
When using litex.gen.sim (instead of migen sim) it would be helpful to be able to generate a gtkw safe file for FSM states, etc. Currently only the soc does this,...
Allows the target soc to override memory initialization: rom and/or ram. Includes documentation for example usage to compile soc target specific software and load it to main_ram. This mechanism can...
Improvements to LiteXArgumentParser when using set_defaults() in a target to ensure args_fill() for the new cpu_type is called and to report using set_default(arg=default) for an argument that doesn't exist.
This change imports test_targets from litex_boards to verify litex changes do not break those targets.
Various enhancements to reduce boilerplate code in target arguments and to cleanly allow a target to initialise memory with a custom firmware (for example). Custom firmware example: class MySimSoC(SoCCore): def...
This is a proof of concept to add a Tristate override to gen/sim/core. It is usable with with the python passionate but untested with verilator, so might need to be...
This set of changes follows on from #1972, #1973, #1974 and adds a mechanism to specify DTS information for a core from anywhere within litex. With these changes we can...