AndrewD

Have you gone any further with this yourself since this proposal? We are interested to use device tree with nuttx in a product and have cloned your fork referenced in...

I'm integrating a VHDL module into litex that uses generics - any pointers to if this is a relatively isolated issue I can look in to in the GHDL plugin?...

@acassis it's an fantastic exercise that people have added Z80 to LLVM as a target architecture. This is way more than I are proposing :) To be clear: our interest...

> Yes, it's always good to update libcxx/libcxxabit to the last official release and remove the temp patch, could you send a PR? While we had a quick look in...

What is your trigger condition for litescope_cli: the aw channel matching the full address? Maybe add a control signal too and trigger on that?

Which cpu did you build your target with? What do you get if you use make.py to automate the linux-on-litex-vexriscv build?

Follow the instructions here: https://github.com/litex-hub/linux-on-litex-vexriscv. This is a supported board: $ ./make.py --board=sipeed_tang_primer_20k --build There are a few other steps, but once you have the default, supported, setup working you...

Thanks - that should address the issue. On Tue, 23 Jan 2024 at 04:41, Gwenhael Goavec-Merou < ***@***.***> wrote: > Hi, > True: CSR region is a bit small. >...

I did something like this a while ago (pre antmicro), see https://github.com/AndrewD/litecan https://github.com/AndrewD/linux-on-litex-vexriscv There was some discussion about changes required for integration a while ago.

Yes, we want this upstream too, i just haven't been focusing on it recently.