litex/gen/sim: add generate_gtkw_savefile() as per simsoc to VCDWriter or Simulator

[AndrewD]

When using litex.gen.sim (instead of migen sim) it would be helpful to be able to generate a gtkw safe file for FSM states, etc.

Currently only the soc does this, but a module unit test is generally just the module, not a "full" soc. Unit tests appear to default top using run_simulator() from migen instead of run_simulator from litex.gen.sim, but if using litex.gen.sim FSM states are not decoded.