André Sintzoff

> ❌ failed run, report available [here](https://riscv-ci.pages.thales-invia.fr/dashboard/dashboard_cva6_2131.html). The added CI job fails due to missing environment variable. It is fixed on Thales CI.

The tarball file contains only files belonging to cva6 repository but not the git repository itself. Therefore no git commands will succeed as there is no git repository in the...

Could you format the Python files with black?

We should not be confused by the similarity between `CV32A60AX` label and `CV32A60X` configuration name. There are few issues with `CV32A60AX` labels. Maybe, it will be reused for the configuration...

Regarding eclipsefdn/eca, it seems there is something wrong with Eclipse site as https://accounts.eclipse.org is not working at all.

As **MBE** belongs to the high part of **mstatus** on RV64 and to **mstatush** on RV32, the behaviour could be different. As **mstatush** is read-only 0 on RV32 CVA6 configurations,...

Thanks for the review. A comment to explain how the RISC-V ISA manual tailored for CV32A60X is generated. The source files from [riscv-isa-manual](https://github.com/riscv/riscv-isa-manual) to be tailored are copied and modified...

I'm wondering if splitting the verification work in multiple sub-projects would be an efficient way to proceed. Such split will introduce the risk of fragmentation if managed by several projects....

Could you propose a clean pull request without commits adding/removing debugging statements and white spaces?

Could you propose a clean pull request without commits adding/removing debugging statements and white spaces?