Error in `make fpga` of official release cva6-5.0.1

[0ena]

Is there an existing CVA6 bug for this?

• [X] I have searched the existing bug issues

Bug Description

Hi,

I have downloaded the latest release of the CVA6 source code from here: https://github.com/openhwgroup/cva6/releases/tag/v5.0.1

and I am trying to do a test run by creating a bitstream, by running make fpga

However the command fails, complaining about missing files

Makefile:46: must set CVA6_REPO_DIR to point at the root of CVA6 sources -- doing it for you...
Makefile:143: XCELIUM_HOME not set which is necessary for compiling DPIs when using XCELIUM
Traceback (most recent call last):
  File "util/flist_flattener.py", line 75, in <module>
    parseFlist(args.inFlist, args.outFlist, args.print_incdir, args.print_newline)
  File "util/flist_flattener.py", line 41, in parseFlist
    raise (RuntimeError(f'{includedFilename} not found'))
RuntimeError: /MY_PATH/cva6-5.0.1/core/cache_subsystem/hpdcache/rtl/hpdcache.Flist not found
make: *** No rule to make target /MY_PATH/cva6-5.0.1/corev_apu/register_interface/src/reg_intf.sv', needed by 'fpga'.  Stop.

Is this supposed to happen with the official release code? How can I fix this? I am using the CVA6 for a project I am building and I would like to tie my project to the latest official release of CVA6.

Thanks!