André Sintzoff
André Sintzoff
see The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 20211203 3.1.1 Hardware Performance Monitor All counters should be implemented, but a legal implementation is to make both the...
### Is there an existing core-v-verif task for this? - [X] I have searched the existing task issues ### Task Description Run randomly generated tests by core-dv (riscv-dv) using custom...
### Is there an existing core-v-verif task for this? - [X] I have searched the existing task issues ### Task Description UVM agent behaving as a coprocessor with dedicated custom...
**Test case** ```systemverilog function automatic logic [$clog2(my_pkg::CONST_A):0] failing_format(input logic [my_pkg::CONST_A:0] in); return 0; endfunction ``` **Actual output** ```systemverilog function automatic logic [$clog2(my_pkg::CONST_A):0] failing_format(input logic [my_pkg::CONST_A:0] in); return 0; endfunction toto.sv:...
**Test case** ```systemverilog module foobar(); if (foo) begin end // foo // foo // foo else begin end endmodule ``` **Actual output** ```systemverilog $ verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format foo.sv module foobar(); if (foo)...
### Is there an existing CVA6 task for this? - [X] I have searched the existing task issues ### Task Description Use verible to lint RTL located in `cva6/core` directory...
### Is there an existing CVA6 task for this? - [x] I have searched the existing task issues ### Task Description Add CSR spec for embedded configuration ### Required Changes...
### Is there an existing CVA6 task for this? - [X] I have searched the existing task issues ### Task Description In current version of CVA6, for interrupts, vector mode...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description According to RISC-V ISA specification, for RV32, the bit...
### Is there an existing CVA6 task for this? - [x] I have searched the existing task issues ### Task Description Write PMP DV plan for embedded configuration ### Required...