André Sintzoff

> Hi @ASintzoff, when you say "Run random generated tests", do you mean test-programs randomly generated by corev-dv (riscv-dv)? Updated description.

> Hi @ASintzoff, I forgot to ask, which version of VCS are you using? Q-2020.03-SP2-1

> @ASintzoff @MikeOpenHWGroup I do not have access to VCS to try this, but this recoding appears to still work in Xcelium: > > ``` > cross_rd_rs1_rs2: cross cp_rd, cp_rs1,...

> ### Issue Type > ### Suggested resolution > > Asking to Synopsys to fix VCS will take a long time. Perhaps we can modify the code to accomplish the...

Before creating a pull request, I would like to be complete. Other constructions using `with` not working with VCS exist in the file. To summarize all of them, are such...

> Agree with @strichmo that `ifdefs` should be a last resort, but it seems we cannot make progress without them. So I propose that we use them on the [cva6/dev...

As @sjthales (developer of Sv32 MMU) is far more competent than me on this topic, I let him tackling the issue. Thanks.

The CSR reset values in https://github.com/openhwgroup/cva6/blob/master/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst were provided by Jade tool. This file needs to be updated with IPXACT generated file.

As the push/pop instructions are transformed into a series of store/load instructions, what is the expected behaviour when an interruption occurs during the execution of the series of store/load instructions?...

As the push/pop instructions are transformed into a series of instructions and as these instructions are going through the issue, the execute and the commit stages, `minstret` CSR will be...