Adrian Sampson

That sounds cool. Ideally, down the road, this could even mean that a fixed-size systolic array could process variable data sizes (i.e., with a run-time-specified loop bound).

That was the notion we discussed briefly about a "final-stage" cleanup to eliminate parts of guards like `& 1` that are artifacts of earlier passes.

Indeed! One baby step we could take here would be reimplementing the `std_mem_d*` components in pure Calyx, which would let us remove the primitives while preserving compatibility… except that we...

Just to fill out the design space, another option would be to extend the language to have multiple, named `control` programs for each component. We would then need a way...

Maybe one way of putting it is that the `kernel.xml` file *describes* what's going on in the Verilog. One thing that's still unclear to me is where the width 512...

Aha, thanks for the correction, @andrewb1999!! That would explain it.

Yes! It does seem like static vs. dynamic slices should probably be different primitives altogether. Static slices would get their indices as meta-level parameters, while dynamic slices would get their...

Thanks for noting this future work down! I just wanted to point out that at least the "ID attributes" thing could be addressed by a broader refactoring to support these...

This is really exciting! I would love to chat more about this; it seems potentially _really_ useful. The vision exactly as @andrewb1999 & @rachitnigam lay it out here sounds perfect...

Indeed, good questions. Building off of @rachitnigam's answer, here's one plausible way to draw a roadmap: 1. Start with the AOT version, and include a "name mangling" scheme for representing...