Adrian Sampson

FWIW, my understanding is that using LUTs and stuff is a subsequent step called "technology mapping" (which happens before placement and routing), but Luis is the expert. (For tangential context,...

Cool! Maybe sometime this or next week would work for folks? (Perhaps we should take this to Slack.)

Aside from the practical issue of supporting more realistic memories, it's an intriguing idea to make memories more "normal," i.e., to make it so using a memory is more like...

This is a good idea IMO. Just a couple of disconnected thoughts: - Add this to the list (with resource sharing & register minimization) of passes that ideally want some...

Yeah, this—defining a policy for when/how to insert this stuff—is a hard question. It reminds me, in a weird way, of having global state… nobody "owns" these signals and they...

Ah yeah, right, implicitly inserting those during _parsing_ is pretty funky. We could shift policies to say that they get inserted at the very end of lowering instead, and components...

Right; that makes sense. I wonder if those two sets of ports (`go` and `done`, which we actually have to do stuff with, and `reset` and `clk`, which we mostly...

Interesting idea! Linking to some background on the overall design space for `par`: #921 & #932 The way I see it, randomization of parallel interleaving is a "cheap" alternative to...

While interesting, this pass has one tricky aspect to it: it would need to make assumptions about the individual components involved. For example, if a 32-bit adder is connected to...

Yep, I think @cgyurgyik diagnosed it right! To put it even more simply, the predicate `i0.out