Adrian Sampson

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Very much in agreement with this: > I think it makes sense to want to implement as much as possible in Calyx, but I wonder if this will increase the...

Just looking around for advice about clock gating and FPGAs in particular, I found [this post](https://zipcpu.com/blog/2021/10/26/clkgate.html) on the always-helpful ZipCPU blog. It confirms what we'd surmised about FPGAs coming with...

Indeed, I think that is only a concern in the ASIC (not FPGA) case. In that case, it's worth going back to thinking about the construction of a basic [D...

Yes indeed! I think it would be cool to add this in another stage in the language tutorial… it could be kinda contrived, but we could just add a phase...

Interesting point! Yeah, maybe that should indeed be the default… if for no other reason than "Verilator and interpreter modes match" is a pretty desirable property.

Good question—in fact, `--raw` is an argument to the actual interpreter executable. So if you were to run that directly (not through fud), you would use `--raw`. To pass this...

Huh, this is a thought-provoking idea! It would be fun to chat sometime in a little more detail with @vegaluisjose included. I think the questions about the scope for Calyx...