Optimizations

[sgpthomas]

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FuTIL optimizations

• [x] Redundancy elimination (#141)
• [x] Static Timing (#154)
• [x] Resource Sharing
• [x] Pipelining (#200)
• [x] Bitwidth analysis (#198)
• [ ] Control pipelining (#382)

Verilog optimizations

• [ ] Don't generate priority logic for muxes. (See writeup) (https://github.com/cucapra/calyx/issues/1423)
• [ ] Generate one-hot encoded FSM (See reasons, more explanation about FSM coding style)

[rachitnigam]

What's "redundancy elimination"?

[sampsyo]

That was the notion we discussed briefly about a "final-stage" cleanup to eliminate parts of guards like & 1 that are artifacts of earlier passes.

[rachitnigam]

Created separate issues for resource sharing (#197) and bitwidth analysis (#198). The others are either not optimizations (pipelining) or unclear how to implement them (control pipelining).

[rachitnigam]

Added one-hot encoding optimization for generated FSMs.