cortex-m
cortex-m copied to clipboard
rust-embedded
Low level access to Cortex-M processors
The ITM can easily be enabled using OpenOCD but that requires having a debugger connected to the MCU. ITM can be used for logging or as a communication channel in...
Is it planned (or even desirable) to switch the `Mutex` implementation from the `bare-metal` import (for use with `interrupt::free`) to one using new [`mutex-trait`](github.com/rust-embedded/mutex-trait) and encapsulating `interrupt::free`? #9
## Background ### Private Peripheral Bus (PPB) All the peripherals in the `cortex_m::Peripherals` struct sit on the Private Peripheral Bus and have addresses of the form `0xE00x_xxxx`. Most of these...
What is the recommended way to access the IPSR (interrupt program status register)? Apparently it used to exist a long time ago and vanished in commit 251d1aa11244d5356659ccf969e29b0e7da82c7a never to be...
As discussed in https://github.com/japaric/cortex-m-rt/issues/44, cortex-m should provide a clean and safe interface for user configurable exceptions, for CM0 those are `SVCall`, `PendSV` and `SysTick`; potentially there're others and/or more for...
How many cycles `asm::delay()` can be affected by how the chip memory is configured and even where the function ends up in Flash. The code assumes the loop takes 4...
If you supply a target as a JSON file, the build.rs can't detect the target. This is because `target` is a full path - in my case starts this starts...
right now you can write any `u32` in the peripherals' registers. This is bad because you may write `1`s to reserved bits that are supposed to always be set to...
`src/peripherals` is pretty much undocumented in this regard.
The `SYST.set_reload` takes a number of cycles as an argument. Even though the type of this argument is an `u32`, only values that fit on 24 bits are valid. The...
