cortex-m
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rust-embedded
Low level access to Cortex-M processors
Lots of lints seen in https://github.com/rust-embedded/cortex-m/pull/590/checks?check_run_id=40591927014. The codebase could use a tidy up.
In the `cortex-m-rt` docs it recommends PACs create a `Vector` type like so: ```rust pub union Vector { handler: unsafe extern "C" fn(), reserved: usize, } ``` and this is...
I have the following signature for my `HardFault` handler: ```rust #[exception(trampoline = false)] #[naked] unsafe fn HardFault() -> ! { ... ``` This triggers the compiler warning > warning: Rust...
Good evening ! I'm starting to use rust+cortex-m on STM32, and I'm planning to mix existing C code (using STM32CubeIDE, CMSIS and freeRTOS) and Rust code (as a static library)....
In addition to the issue described in #499, note that the ICSR VECTACTIVE/VECTPENDING bits, as well as the similarly-encoded exception bits in the xPSR, are _nine bit fields,_ so a...
