cortex-m
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rust-embedded
Low level access to Cortex-M processors
cortex-m-rt 0.7.4 changes the exception macro so that hardfaults now have an *optional* trampoline argument. If the argument isn't given, the exception frame reference isn't passed. Unfortunately the macro crate...
Implements coprocessor basic access instructions (MCR, MRC, MCRR, MRRC) that compile to a single instruction under `--release` profiles
Just ran into this while trying to generate a PAC, this fixes #529 . Not sure if it would be better to change the default value to 496 as well.
The current wording implies the next call to `has_wrapped()` after `clear_current()` always returns false. According to the arm docs this is not always true: 
This PR ports some of the ongoing work in the RISC-V ecosystem to Cortex-M targets. Namely, I adapted the `riscv-pac` crate to the new `cortex-m-pac` crate. The main purpose of...
So I spend a while figuring out why my interrupts weren't working and it seems like I wasn't the first. I think `cortex_m::asm::bootload` should at least mention setting VTOR in...
This adds a function to switch to program stack and unprivileged mode. Fixes #583
Hello all, I am experimenting with an STM32F303 and try to enter unprivileged mode with program stack pointer set. I use the following minimal example: ``` #![no_std] #![no_main] use panic_halt...
In https://github.com/rust-embedded/cortex-ar, there is a crate called [`arm-targets`](https://docs.rs/arm-targets) which sets up cfg's for all kinds of Arm targets. The `cortex-m` crate could use that rather than doing its own thing.
