Rachit Nigam

I would not allow for the `QuertType::Port` at all because that would tie us to a particular FSM implementation strategy. For example, if we want to internally generate multiple registers...

BTW, I should mention that this is super exciting overall! Thanks for writing up the issue. I think there is a lot of room for cool stuff. I'll add two...

I would go ahead and implement a prototype if you have a good sense of what to do @calebmkim and we can discuss it in a future Calyx meeting.

Super exciting stuff! > we could store the query in a register rather than checking the FSM value directly I'm not sure what this would look like? Are you saying...

Interesting stuff @parthsarkar17! As always, I think it is going to be hard to judge the impact of some of these optimizations without implementing and trying them out with the...

Oh, this is an awesome insight! We can generalize and maybe hide away `new_fsm` with this kind of reasoning!

One thing to be careful about is not introducing extra latency for FSMs that represent a loop.

Hey @anthonyabeo! This one is a little tricky because we need to document a bunch of internal policies. I would recommend working on something else instead.

I think long term maybe we want this to be explicit (`a{..}`) and have a better error message? I thin the `a = b` syntax is a little tricky because...

Looks cool! What is the game plan with this?