litghost
litghost
To be clear, BRAM36's are exposed in FASM as 2 BRAM18's. If you repeat the design using only BRAM18's, do you observe the same error? How confident is your mapping...
I need the DCP from your replication, or your exact TCL script and Vivado version used.
Tile `BRAM_R_X47Y40` is not part of the 50T fabric? Exactly which part are you testing on?
I assume `BRAM_R_X47Y40` is a typo, and you meant `BRAM_R_X37Y40`?
The problems appears to soley about **all** BRAM_R tiles. BRAM_L tiles operate per the database. As a short term solution, you can set prohibit on sites located within BRAM_R tiles,...
At a minimum, the top 128 bits INIT_3F of BRAM_R (and the top bits of the high INITP) appear to have problems. If I had to guess, the problem lies...
> So, are you saying the BRAM_R are not supported yet? If you can avoid needing to set INIT_3F[255:128] or INITP_07[255:128], then I expect things work as expected.
@tmichalak I believe that bitread is missing some bits at the end of the bitstream. [bram_demo.tar.gz](https://github.com/SymbiFlow/prjxray/files/4503851/bram_demo.tar.gz) Replication, using Vivado's rbt output (with the `-raw_bitfile` flag): ``` # diff build_xc7a50tfgg484-1/specimen_001/design.rbt build_xc7a50tfgg484-1/specimen_002/design.rbt...
Can you be more concrete? Neither setup.py nor requirements depend on yosys.
I'm not familiar with your use of the word "vendored" in this context. What do you mean?