litghost

> By disabling the pip loop that extracts all pips related to a tile, run-time dropped from `~44 minutes` to `~8 minutes` for the zynq7010. Try dropping anything that uses...

> @litghost That was the right call, run-time is now `~13 minutes` for the tiles job Ok, so rather than writing out the full timing info, just write the speed...

> So this would suggest a pin in the HP bank should never be LVCMOS33 or LVCMOS25. Agreed. The question is whether there are packages that use something other than...

> Can we estimate the bitstream size from the number of CLB, DSP, and BRAM columns required for a reconfigurable block？ Such an estimation should be possible, but no one...

- CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF - CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.INTERNAL These were intentionally removed - CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 - CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 These are still present? - LIOB33.IOB_Y0.LVCMOS15.DRIVE.I4 - LIOB33.IOB_Y0.LVCMOS15.IN These are likely an instability in the fuzzer.

FYI: @nelsobe / @mithro

I've updated this with a new schema that finds "Maximum Edge Cardinality Bicliques" and then does a greedy set cover to select the bicliques. Given that both maximum edge biclique...

@nelsobe Can you find someone to review this?

If you run $XRAY_BIT2FASM --verbose, and grep the output for "unknown", do you find anything?

@nelsobe Have you confirmed that the `INIT_xx` does from the FASM do **not** match the `INIT_xx` parameter from the relevant RAMBx cells in Vivado?