litghost
litghost
> > I don't remember, but I believe this was not enough for LDCE support. In general, latches are not something that should be present in pure FPGA designs, so...
There is a prjxray fuzzer [here](https://github.com/SymbiFlow/prjxray/pull/1185) that might help. However the fuzzer was never stabilized, and was not merged. @daveshah1 expressed interest in that PR getting finished up, but to...
@mithro I'm inclined to close this PR?
@mithro I'm inclined to close this PR?
@ethanroj23 Can you fix you DCO? E.g. use `git commit -s" on your commits.
It's not clear from you data, but do your method allow fast lookup of node to wire and wire to node? From glancing at your data, it doesn't appear so?
> @litghost I don't think it does at this point. I think that means that you data size comparison is incorrect. I believe you have only implemented `Node to wire...
> @ethanroj23 Can you fix you DCO? E.g. use `git commit -s" on your commits. DCO is still incorrect, please fix: https://stackoverflow.com/questions/25570947/how-to-use-git-interactive-rebase-for-signing-off-a-series-of-commits Stack OverflowHow to use git interactive rebase for...
Looks like the node job time is pretty small compared to the tiles job time, so that is where we should look for issues.
> We could extract the tiles from 1 or 2 clock regions, maintaining the run-time constant with the change of the part. I need to verify whether this is doable...