litghost
litghost
The Vivado net convention is to name the net after the driver wire. Net's other than the driver net "parent" to that net.
It is a little suspicious that the clock for that RIOI3 is coming from the interconnect, though I do agree the bits are missing. We should likely investigate adding the...
When writing a test for #9, I hit https://github.com/YosysHQ/yosys/issues/1720 . Until https://github.com/YosysHQ/yosys/issues/1720 is fixed, working on tests downstream of yosys doesn't make a ton of sense.
> We need to make sure commands that are not number will error out. Also if a number if supplied with more arguments. So examples: ``` [0] -> [0] [0...
Also we discussed having an option on `read_xdc` to control whether the behavior is a warning or an error.
> As the resolution says, it may be necessary to get first all the BEL constraints defined and later all the LOC constraints. This would likely double the size of...
> New issue found when running with the updated fasm2bels library the blinky test: > > ``` > WARNING: [Vivado 12-1023] No nets matched for command 'get_nets -of_object [get_pins {*CLBLM_R_X39Y73_SLICE_X60Y73_CARRY4/CO[3]}]'....
The error above looks like the CARRY4 at CLBLM_R_X39Y73.SLICEM_X0 is missing. The Verilog you pasted is missing a "LOC=" annotation.
> Actually the LOC should be in the XDC. Good point.
> 1. BRAM sinks cannot be connected to their sources. The output below is obtained by allowing orphan sinks: These may be nextpnr bugs, if nextpnr is not routing the...