Vitis-Tutorials

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ERROR: [v++ 60-602]

5

Hi, I am facing a problem when i build vector addition application project. I can build with Emulation-SW, but when I tried to build with Emulation-HW or Hardware. I got...

canozcifci

unable Export Hardware XSA as Vitis Custom Embedded Platform Creation Example on KV260

6

``` INFO: [Project 1-1042] Successfully generated hpfm file unmatched open brace in #list ERROR: [Common 17-69] Command failed: unmatched open brace in list ``` vado2021.1 Vi   ...

dongzhang2021

Getting_Started ZCU102 error. cannot boot on ZCU102 with "Kernel panic - not syncing: VFS: Cannot open root device "mmcblk0p2" or unknown-block(179,2): error -6"

8

Dear Authors, I have followed the steps and generated the sd_card folder successfully. However, I cannot boot the Linux system on ZCU102 via sd_card. This is some error information when...

sunhao-seu

The Getting-Started app.exe segfaults on XRT 2.13.0

7

I tried the getting started example on my Varium C1100 aka u55n: https://github.com/vkomenda/Vitis-Tutorials/tree/u55n-getting-started/Getting_Started/Vitis/example/u55n I have neither u200 nor zcu102 to compare with. The XRT version is 2.13.0 from the Git...

vkomenda

Pre-synthesis Control Flow Error occurred after running C simulation

3

After I ran the C simulation on the synthesis and analysis part of the Vitis HLS Getting Started tutorial, the dct_csim.log gave TEST PASSED, but the Pre-synthesis control flow did...

CoffeeCat3008871

Vitis Custom Embedded Platform Creation Example on ZCU104 DPU Test 3: Run a Vitis-AI Demo not working

8

Hi, I've gone through this tutorial with Vitis 2020.2 and Vitis AI v1.3 : [https://github.com/Xilinx/Vitis-Tutorials/tree/2020.2/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104](https://github.com/Xilinx/Vitis-Tutorials/tree/2020.2/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104) With some slight differences: 1. My Vitis platform has a MIG IP core for interfacing...

Ali-Flt

Problem with depth in Hardware kernel code of Vitis-Tutorials/Hardware_Acceleration/Design_Tutorials/01-convolution-tutorial

4

Hi, I've read the whole tutorial and understood all of it. But an issue I have is that the depth of output_stream in the top-level function of the [filter2d_hw.cpp](https://github.com/Xilinx/Vitis-Tutorials/blob/2021.1/Hardware_Acceleration/Design_Tutorials/01-convolution-tutorial/src/filter2d_hw.cpp) file...

Ali-Flt

Embedded Design Tutorials/Zynq UltraScale+ MPSoC Embedded Design Tutorial/Design Example 1: Using GPIOs, Timers, and Interrupts/ can't open The "ref_design" example URL

1

LoeWHJ

makefile and readme needs modification

1

https://github.com/Xilinx/Vitis-Tutorials/blob/master/AI_Engine_Development/Design_Tutorials/01-aie_lenet_tutorial/Makefiles/Makefile Line 63, SYSROOT_PATH needs to be changed with the path to xilinx-versal-common-v2020.2 at user's end. This should be added to Readme. Line 247, --package.sd_dir $(PLATFORM_REPO_PATHS)/sw/versal/xrt This line should be...

vivianyin

RTL Simulation runs fail for VADD RTL Tutorial

2

Hi when I follow up the tutorial here for running the RTL simulation: [instructions:](https://github.com/Xilinx/Vitis-Tutorials/blob/2020.1/Hardware_Accelerators/Feature_Tutorials/01-rtl_kernel_workflow/vivado_ip.md) I get below error: `ERROR: [VRFC 10-2989] 'axi_vip_pkg' is not declared [/home/xeniro/vivado_prj/rtl_kernel/rtl_kernel.srcs/sources_1/imports/src/testbench/Vadd_A_B_tb.sv:6] ERROR: [VRFC 10-2989] 'slv_m00_axi_vip_pkg'...

lmaxeniro