Vitis-Tutorials

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AI Engine GMIO Performance Profile: Measurements using timer do not provide the listed performance

2

** Which tutorial are you running? ** https://github.com/Xilinx/Vitis-Tutorials/blob/2022.2/AI_Engine_Development/Feature_Tutorials/02-using-gmio/perf_profile_aie_gmio.md using macro __TIMER__. ** Describe the issue ** Measurements using timer do not provide the listed performance. I measured it twice, and...

satoru-i

** Which tutorial are you running? ** Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/09-using-ethernet-on-alveo. ** Describe the issue ** The x1 example works correctly but when changing the lanes to x4 the bitstream generation fails: ===>The...

ash8327

Vitis_Platform_Creation/Feature_Tutorials/02_petalinux_customization: ZCU104 yocto-machine name invalid

1

** Which tutorial are you running? ** Vitis_Platform_Creation/Feature_Tutorials/02_petalinux_customization ** Describe the issue ** Configuration of yocto-machine name "zcu104-zynqmp" is invalid. There is an error occuring : rsync: link_stat "/tools/petalinux-v2022.1-final/components/misc/yocto_machines/zcu104-zynqmp.conf" failed:...

Spartak0s

Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104: Petalinux Makefile not works as expected on Readme.md

1

** Which tutorial are you running? ** 2021.2/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104 ** Describe the issue ** The command on line 72 of makefile (https://github.com/Xilinx/Vitis-Tutorials/blob/2021.2/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104/ref_files/step2_petalinux/Makefile#L72) is bypassing the previous update on rootfs_config https://github.com/Xilinx/Vitis-Tutorials/blob/2021.2/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104/ref_files/step2_petalinux/Makefile#L70 ....

Spartak0s

Checking timing violation path

5

I have received negative slack for my kernel. Is there any way to identify logic path causing the timing violation from the Vitis HLS GUI? I feel like I have...

m-kru

10-aie-dsp-lib-model-composer: Facing compilation errors while generating hardware image for the 10-aie-dsp-lib-model-composer tutorial

3

** Which tutorial are you running? ** I'm running **Designing with the AI Engine DSPLib and Vitis Model Composer**(_https://github.com/Xilinx/Vitis-Tutorials/tree/c2e1a5d0caff6a2ec0bb196d0d807d733f9d0c3d/AI_Engine_Development/Feature_Tutorials/10-aie-dsp-lib-model-composer_) tutorial. ** Describe the issue ** I was successfully ran the...

Hari-MathWorks

Burst Understanding (Generic Question)

1

I saw in file Vadd_A_B.v in tutorial [01-rtl_kernel_workflow] that burst is recommended to be incremental only, why incremental is recommended and Can i use fixed burst ?

MahmoudElShimy96

Multiple AIE kernels in same .cc file

3

Hi, I was looking at the LeNet AIE tutorial and have the below queries **Each kernel is defined in a separate .cc file** 1. What is the motivation behind it?...

praveen0447

Different LUT utilization in the System Diagram and Utilization tabs

2

I have compiled and linked some custom kernel. When I view the report, using Vitis Analyzer, I can see different utilization information in the `System Diagram` tab and in the...

m-kru

How to benchmark AI Engine code on hardware

4

Hello Everyone, I would like to benchmark the AI Engine code on the hardware. Can anyone let me know, any XILINX tool that used for timing the CODE that running...

nhkrishna