Vitis-Tutorials
Vitis-Tutorials copied to clipboard
Xilinx
Vitis In-Depth Tutorials
I am working on adding more iterations to this tutorial. however I have been facing design timing problem when more iterations are added to PL kernels. For example, I added...
I move the "Vitis_Libraries" to "Hardware_Acceleration/Introduction/design_source/hw_src/" and executed the "make" command. Then the error occurs： ERROR: [v++ 207-3334] no matching function for call to 'resize' (/home/foxken_zxl/Vitis-Tutorials/Hardware_Acceleration/Introduction/design_source/hw_src/resize_rgb.cpp:77:9) I did not change...
We have a vck5000 development card installed on the server. According to the public available tutorial, I tried to deploy some simple application algorithms onto vck5000. Currently I am able...
Hi, I was trying to create a new application project in vitis and I encountered this issue. I never had this issue before while creating an application project with the...
Hello, I follow the tutorials (https://github.com/Xilinx/Vitis-Tutorials/tree/2021.2/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104) and change board information from ZCU104 to ZCU106 in step1 and step2 and step3. However, when I test the platform in step4(test vadd), I...
This makes the moving with Alveo example work with the 2023.2 tools and the existing Makefile.
Hi https://github.com/Xilinx/Vitis-Tutorials/tree/2023.2/AI_Engine_Development/AIE/Feature_Tutorials/07-AI-Engine-Floating-Point#fpneg_mul and https://github.com/Xilinx/Vitis-Tutorials/tree/2023.2/AI_Engine_Development/AIE/Feature_Tutorials/07-AI-Engine-Floating-Point#fpneg_abs_mul Present the same function signature, description, and code example, which is not expected as far as I understand.
Vitis-Tutorials/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization
The command "make OPT=0 all_hw_emu" as given in the tutorial doesn't work. Probably the command "build_hw_emu" sould be used instead.
Hello, I am encountering an issue while using **hls::stream** as an intermediate variable in my project. **The compiler is indicating that the bit width is too large, exceeding the 4096...
 This diagram implies the more you cascade, the higher throughput per cascade length because the slope is steeper. However, according to the numbers, the more you cascade, throughput per...
