Vitis-Tutorials
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Xilinx
Vitis In-Depth Tutorials
Hello Everyone, I'm trying out the 2022.2 version [01-aie_lenet_tutorial](https://github.com/Xilinx/Vitis-Tutorials/tree/2022.2/AI_Engine_Development/Design_Tutorials/01-aie_lenet_tutorial). I was able to build the example and successfully deployed on to the hardware. Thanks for the detailed steps in the...
**Describe the issue** I was able to successfully run the "**13-aie-performance-analysis**" on both Hardware emulation and actual hardware with out any modifications. But If I use the `event::start_profiling(gr.in, gr.dataout, event::io_stream_start_difference_cycles)`...
``` WARNING: unilog-1.4.0-r0 do_fetch: Failed to fetch URL git://[gitenterprise.xilinx.com/aisw/unilo](https://gitenterprise.xilinx.com/aisw/unilo) g.git;protocol=https;branch=dev, attempting MIRRORS if available ``` The SState-Cache URLs seem to be missing from the last few days. Please update as...
Hi, I am trying the 2022.2 version of AIE FIR tutorial on an emulator. I was able to create the application and xclbin with the steps mentioned in the [link](https://github.com/Xilinx/Vitis-Tutorials/tree/2022.2/AI_Engine_Development/Design_Tutorials/07-firFilter_AIEvsHLS/AIE)....
Hi, I am using iwave's zu19eg development kit, I was trying to implement the vitis based designs on hardware. I started with basic vector_add code. When i am running the...
Hi, I'm following the KV260 tutorial and am seeing the following error when trying to generate the device tree. I'm running 2022.1 on Ubuntu 22.04. What am I doing wrong...
Hi I was trying to go thru the 09-Ethernet-Alveo using LANE=4 However, vitis was not able to complete the implementation and leaving an error of below [Constraints 18-1000] Routing results...
These lines reference host.cpp in the wrong directory (should be `../src/host.cpp`) https://github.com/Xilinx/Vitis-Tutorials/blob/6cc013da57c88e9aedf09cbcc385a3f78556190f/Getting_Started/Vitis/Part4-data_center.md?plain=1#L60 https://github.com/Xilinx/Vitis-Tutorials/blob/6cc013da57c88e9aedf09cbcc385a3f78556190f/Getting_Started/Vitis/Part4-data_center.md?plain=1#L132 https://github.com/Xilinx/Vitis-Tutorials/blob/6cc013da57c88e9aedf09cbcc385a3f78556190f/Getting_Started/Vitis/Part4-data_center.md?plain=1#L160 --- Likewise for u250.cfg here https://github.com/Xilinx/Vitis-Tutorials/blob/6cc013da57c88e9aedf09cbcc385a3f78556190f/Getting_Started/Vitis/Part4-data_center.md?plain=1#L162 --- u250_hls.cfg doesn't exist. It should be `../src/u250.cfg` https://github.com/Xilinx/Vitis-Tutorials/blob/6cc013da57c88e9aedf09cbcc385a3f78556190f/Getting_Started/Vitis/Part4-data_center.md?plain=1#L134 https://github.com/Xilinx/Vitis-Tutorials/blob/6cc013da57c88e9aedf09cbcc385a3f78556190f/Getting_Started/Vitis/Part4-data_center.md?plain=1#L161...
Had this for my Ubuntu system trying to compile the simple AIE-ML example. This fixed it: ln -s /usr/include/asm-generic /usr/include/asm
I'm struggling to find documentation and tutorials for using Vitis 2.5 AI Optimizer to prune custom PyTorch neural networks. Despite searching through official documentation and GitHub tutorials, I haven't found...
