Vitis-Tutorials icon indicating copy to clipboard operation
Vitis-Tutorials copied to clipboard

Published 20 hours ago • verified publisher icon Xilinx

Pre-synthesis Control Flow Error occurred after running C simulation

Open CoffeeCat3008871 opened this issue 4 years ago • 3 comments

After I ran the C simulation on the synthesis and analysis part of the Vitis HLS Getting Started tutorial, the dct_csim.log gave TEST PASSED, but the Pre-synthesis control flow did not show up and an error occurred in the problem console as the followings:

Error_1 Error_2

CoffeeCat3008871 avatar Oct 29 '21 13:10 CoffeeCat3008871

Same problem reported on Xilinx forum, but not solved.

danna2019 avatar Oct 30 '21 01:10 danna2019

Can you post your operating system information here?

randyh62 avatar Oct 30 '21 20:10 randyh62

image

CoffeeCat3008871 avatar Oct 31 '21 04:10 CoffeeCat3008871

Hi all,

Is there any update regarding this issue? I am having the same problem in Vitis HLS 2020.2 on Ubuntu 20.04.6 LTS.

lefmylonas avatar Apr 06 '23 10:04 lefmylonas

The issue appears to be something related to the environment or system setup. I was not able to recreate the problem described above. Can you share any additional information related to your environment?

randyh62 avatar Apr 06 '23 16:04 randyh62

Hi again and thank you for the quick reply!

Actually i found the problem in my case. There was a problem with my setup. I had to change my default desktop environment with this command "$ sudo update-alternatives --config x-session-manager".

lefmylonas avatar Apr 06 '23 20:04 lefmylonas