zliu1Charlotte

Hi, I have issues when implementing skywater130nm standard cells into level2 mux from k6_N10_40nm.xml ``` ``` I was able to implement k4_n4 arch with skywater but having issues with level...

Hi, I am curious on what is the command for forcing the design to have the shortest routing, also the longest routing? Thanks! I do see there are --place_algorithm {bounding_box...

Unexpected attribute 'tileable' found on node 'layout'

3

this is the command I ran: `~/vtr-verilog-to-routing/vpr/vpr k4_N4_tileable_40nm.xml xor_cipher.blif --clock_modeling route` vpr_arch is from https://github.com/lnis-uofu/OpenFPGA/blob/master/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml it gives error: ``` VPR FPGA Placement and Routing. Version: 8.1.0-dev+f669015f3 Revision: v8.0.0-6941-gf669015f3 Compiled: 2023-02-10T16:13:42...

Dear all, I loaded my post-syn netlist, .sdf, testbench, and skywater cells using modelsim command line. but it seems like my gate-level simulation's inputs and outputs are all remained as...

Is it possible to not have LUT6_2 in the reversed netlist after using fasm2bels, insted generate the netlist using LUT5 and LUT6? Thanks! Also can we generate a sdf file...

Graphics on OpenFPGA?

1

Is openfpga able to generate graphics, such as the picture of place and route, like vpr's graphics command? Thanks!